EPM3512AFC256-10N vs EPM3512AFC256-21 对比

详细并排对比 EPM3512AFC256-10N 出自 Altera 和 EPM3512AFC256-21 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-10N EPM3512AFC256-21
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $43.22 $18.75
Family MAX 3000A —
Macrocells 512 —
Usable Gates 10000 10,000
User I/O Pins 208 —
Logic Array Blocks (LABs) [DATA_NEEDED: number of LABs] 16
Operating Frequency (fMAX) [DATA_NEEDED: fMAX MHz] —
Pin-to-Pin Delay (tPD) 10 ns —
Setup Time (tSU) 4.5 ns —
VCCINT (Core Supply) 3.3 V —
VCCIO (I/O Supply) 3.3 V or 2.5 V —
Technology CMOS EEPROM-based, non-volatile —
Operating Temperature (Commercial) 0 C to +70 C —
封装 256-ball FBGA (17 mm x 17 mm) FBGA-256 (FineLine BGA)
ISP Interface IEEE Std. 1149.1 JTAG, IEEE Std. 1532 —
安装类型 Surface Mount (BGA) Surface Mount (BGA)
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Device Family — MAX 3000A
Logic Elements / Macrocells — 512 macrocells
Maximum Operating Frequency — 87 MHz
工作温度 — -40C to +85C (industrial)
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multi-volt I/O)
Programmable Pins (max) — [DATA_NEEDED: maximum user I/O pin count]
Programming Interface — JTAG / IEEE Std. 1532 ISP
存储器类型 — Non-volatile EPROM/EEPROM cell array
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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