EPM3512AFC256-19 vs EPM3512AFC256-20 对比
详细并排对比 EPM3512AFC256-19 出自 Altera 和 EPM3512AFC256-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 Obsolete规格对比
| 参数 | EPM3512AFC256-19 | EPM3512AFC256-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.85 | $9.75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10000 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 80 MHz | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Speed Grade | -19 | -20 (20 ns tPD) |
| User I/O Pins | 208 | — |
| 封装 | 256-ball FineLine BGA (FC) | 256-ball FBGA (Fine-pitch BGA) |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Supply Voltage VCCIO | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| 工作温度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Non-volatile Configuration | Yes (EEPROM-based) | — |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Typical Usable Gates | — | 10,000 |
| 引脚数量 | — | 256 |
| Operating Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Voltage (VCCIO) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| I/O Standards | — | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant |
| Program Memory Type | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| JTAG Support | — | Yes (boundary-scan + ISP) |
| MSL 等级 | — | [DATA_NEEDED: MSL moisture sensitivity level] |
| Configuration Memory | — | Internal EEPROM |