EPM3512AFC256-2 vs EPM3512AFC256-18 对比

详细并排对比 EPM3512AFC256-2 出自 Altera 和 EPM3512AFC256-18 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-2 EPM3512AFC256-18
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $14.85 $17.20
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 212 212
Propagation Delay (tPD, -2 grade) [DATA_NEEDED: tPD ns] —
Maximum Operating Frequency [DATA_NEEDED: fMAX MHz] —
Core Supply Voltage 3.3 V —
I/O Output Drive Voltage 2.5 V or 3.3 V (MultiVolt) —
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant —
封装 BGA-256 (FineLine BGA) 256-ball FineLine BGA (FCBGA)
Ball Pitch 1.0 mm 1.0 mm
Programming Interface JTAG (IEEE Std 1149.1) / ByteBlaster —
Process Technology 0.30 um CMOS EEPROM —
工作温度 0C to +70C (commercial) [DATA_NEEDED: industrial/commercial grade]
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: not specified in retrieved data]
Speed Grade -2 —
Pin-to-Pin Delay (tPD1) — 18 ns
Global Clock Networks — 4
VCCINT (Core Supply) — 3.0 V to 3.6 V (3.3 V typical)
VCCIO (I/O Supply) — 2.5 V or 3.3 V (MultiVolt)
Programming Technology — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1532 / JTAG (IEEE Std. 1149.1)
安装类型 — Surface Mount

数据手册与资源

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