EPM3512AFC256-23 vs EPM3512AFC256-2 对比
详细并排对比 EPM3512AFC256-23 出自 Altera 和 EPM3512AFC256-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 Obsolete规格对比
| 参数 | EPM3512AFC256-23 | EPM3512AFC256-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $15.75 | $14.85 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | 16 |
| Maximum Operating Frequency | 178.6 MHz | [DATA_NEEDED: fMAX MHz] |
| Propagation Delay (tPD) | 5.5 ns | — |
| Pin-to-Pin Delay | 23 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for FC256] | — |
| 封装 | 256-ball FineLine BGA (FC256), 17 mm x 17 mm | BGA-256 (FineLine BGA) |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | JTAG (IEEE Std 1149.1) / ByteBlaster |
| Process Technology | 0.30 µm CMOS EEPROM | 0.30 um CMOS EEPROM |
| 工作温度 | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| 安装类型 | Surface Mount (BGA) | — |
| Maximum User I/O Pins | — | 212 |
| Propagation Delay (tPD, -2 grade) | — | [DATA_NEEDED: tPD ns] |
| Core Supply Voltage | — | 3.3 V |
| I/O Output Drive Voltage | — | 2.5 V or 3.3 V (MultiVolt) |
| Input Tolerance | — | 2.5 V, 3.3 V, 5.0 V tolerant |
| Ball Pitch | — | 1.0 mm |
| RoHS 状态 | — | [DATA_NEEDED: RoHS status] |
| Speed Grade | — | -2 |