EPM3512AFC256-2N vs EPM3512AFC256-7N 对比

详细并排对比 EPM3512AFC256-2N 出自 Intel 和 EPM3512AFC256-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-2N EPM3512AFC256-7N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $25.80 $61.00
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 32 —
Maximum User I/O Pins 212 —
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns] 7.5 ns
Maximum Operating Frequency [DATA_NEEDED: fMAX in MHz] —
Process Technology 0.30 µm CMOS EEPROM CMOS EEPROM, 0.30 um
Configuration Memory Non-volatile EEPROM —
In-System Programmability IEEE Std. 1532 JTAG IEEE Std. 1532 compliant
VCCINT (Core Supply) 3.3 V —
VCCIO (I/O Supply) 2.5 V / 3.3 V / 5.0 V MultiVolt —
PCI Compliance 3.3 V PCI-compliant —
封装 256-ball FineLine BGA (FC-256) 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch
Operating Temperature (Commercial) 0 °C to +70 °C —
RoHS 状态 Compliant [DATA_NEEDED: RoHS status]
Lead-Free Yes —
安装类型 Surface Mount (BGA) Surface Mount
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 10,000
User I/Os — 208
Logic Blocks — 16 (32 macrocells each)
Maximum Internal Frequency (fMAX) — 116.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
5V Tolerant I/O — Yes
Programming Interface — JTAG (IEEE 1149.1)
工作温度 — 0 C to 70 C (commercial)

数据手册与资源

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