EPM3512AFC256-7N vs EPM3512AFC256-19 对比
详细并排对比 EPM3512AFC256-7N 出自 Altera 和 EPM3512AFC256-19 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N Obsolete规格对比
| 参数 | EPM3512AFC256-7N | EPM3512AFC256-19 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $61.00 | $10.85 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10000 |
| User I/Os | 208 | — |
| Logic Blocks | 16 (32 macrocells each) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 5V Tolerant I/O | Yes | — |
| In-System Programmability | IEEE Std. 1532 compliant | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Process Technology | CMOS EEPROM, 0.30 um | 0.30 µm CMOS EEPROM |
| 封装 | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch | 256-ball FineLine BGA (FC) |
| 工作温度 | 0 C to 70 C (commercial) | -40C to +85C (industrial) |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum Operating Frequency | — | 80 MHz |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Speed Grade | — | -19 |
| User I/O Pins | — | 208 |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Supply Voltage VCCIO | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Non-volatile Configuration | — | Yes (EEPROM-based) |