EPM3512AFI256-7 vs EPM3512AFI256-10N 对比

详细并排对比 EPM3512AFI256-7 出自 Altera 和 EPM3512AFI256-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AFI256-10N EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera

EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera

EPM3512AFI256-10N ⚠ 最后一次采购

规格对比

参数 EPM3512AFI256-7 EPM3512AFI256-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $15.95 $21.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 —
Usable Gates 10,000 Up to 10,000
Logic Array Blocks (LABs) 32 (16 macrocells each) —
User I/O Pins 208 —
Pin-to-Pin Delay (tPD) 7.5 ns —
Maximum Operating Frequency [DATA_NEEDED: fMAX value] —
Supply Voltage VCCINT 3.3 V —
MultiVolt I/O Voltage 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant —
Process Technology 0.30 µm CMOS EEPROM —
封装 256-ball FBGA (Fine-Pitch BGA), 17 mm × 17 mm, 1.0 mm pitch 256-ball FineLine BGA (FBGA-256)
In-System Programmability IEEE Std. 1532 compliant via JTAG Yes - IEEE Std 1532 compliant
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) —
Operating Temperature (Industrial) -40 °C to +85 °C —
RoHS 状态 [DATA_NEEDED: confirm from data] Compliant
安装类型 Surface Mount (BGA) Surface Mount
Series — EPM3512
Architecture — CMOS EEPROM-based, MAX architecture
Number of Macrocells — 512
Number of Logic Array Blocks (LABs) — 16
Number of User I/O — 208
Total Pins — 256
Pin-to-Pin Propagation Delay (tPD) — 10 ns
Maximum Counter Frequency — 227.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Supply Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
MultiVolt I/O Support — 5.0 V / 3.3 V / 2.5 V
JTAG Boundary Scan — Yes - IEEE 1149.1
Program Memory — EEPROM (non-volatile)
工作温度范围 — -40 °C to +85 °C (industrial)
Speed Grade — -10 (10 ns tPD)

数据手册与资源

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