EPM3512AQC208-10NS vs EPM3512AQC208-7N 对比

详细并排对比 EPM3512AQC208-10NS 出自 Altera 和 EPM3512AQC208-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ 最后一次采购

规格对比

参数 EPM3512AQC208-10NS EPM3512AQC208-7N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 最后采购期
库存状态 有库存 有库存
单价(USD) $32.40 $41.41
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 512 —
Usable Gates 10,000 —
Logic Array Blocks (LABs) 12 32
User I/Os 172 172
Pin-to-Pin Delay (tPD) 10 ns (speed grade -10) —
Internal Counter Frequency 227.3 MHz max —
Propagation Delay 7.5 ns (datasheet figure) —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
Logic Family CMOS, EEPROM-based —
Configuration Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) Non-volatile EEPROM, in-system programmable (ISP)
封装 208-pin PQFP 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing)
工作温度 0C to +70C (commercial) 0 °C to +70 °C (commercial)
ISP Standard IEEE Std. 1532 —
RoHS 状态 [DATA_NEEDED: rohs status] Compliant
安装类型 Surface Mount —
Logic Capacity — 512 macrocells, 10,000 usable gates
Macrocells per LAB — 16
Propagation Delay (tPD) — 7.5 ns
Maximum Frequency (fCNT) — 116.3 MHz
Supply Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Bank Count — 4 (MultiVolt)
Supported I/O Standards — 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS
Process Technology — 0.30 µm CMOS EEPROM
JTAG Interface — IEEE 1149.1 BST + IEEE 1532 ISP
Speed Grade — -7

数据手册与资源

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