EPM3512AQC208-3 vs EPM3512AQC208-10 对比

详细并排对比 EPM3512AQC208-3 出自 Altera 和 EPM3512AQC208-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AQC208-3 EPM3512AQC208-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $27.80 $22.10
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Logic Array Blocks (LABs) 16 (32 macrocells each) 32
Maximum User I/O Pins 172 —
封装 PQFP-208 208-pin PQFP
Speed Grade -3 —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Bank Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multiVolt) —
In-System Programmability Yes (IEEE Std. 1532 compliant) Yes (IEEE Std. 1532)
Boundary-Scan Test Yes (IEEE Std. 1149.1 / JTAG) —
Program/Erase Cycles 100 minimum [DATA_NEEDED: exact datasheet figure] —
Non-Volatile Configuration Yes (EEPROM-based) —
工作温度 [DATA_NEEDED: industrial/commercial grade range] 0C to +70 C (commercial)
RoHS 状态 [DATA_NEEDED: confirm from datasheet] [DATA_NEEDED: RoHS status not in verified data]
安装类型 Surface Mount —
MSL 等级 [DATA_NEEDED: moisture sensitivity level] —
Usable Gates — 10,000
User I/Os — 208
Propagation Delay (tPD) — 7.5 ns
Maximum Frequency (fCNT) — 116.3 MHz
Supply Voltage (VCCINT) — 3.3 V
Configuration Memory — EEPROM (non-volatile)
JTAG Boundary Scan — Yes (IEEE 1149.1)
PCI Compliance — PCI Local Bus Spec Rev. 2.2 (-10 speed grade)

数据手册与资源

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