EPM3512AQC208-7 vs EPM3512AQC208-7N 对比

详细并排对比 EPM3512AQC208-7 出自 Intel 和 EPM3512AQC208-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ 最后一次采购

规格对比

参数 EPM3512AQC208-7 EPM3512AQC208-7N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $41.72 $41.41
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 —
Usable Gates 10,000 —
Propagation Delay (tPD) 7.5 ns 7.5 ns
Counter Frequency (fCNT) 116.3 MHz —
User I/Os 172 172
Logic Elements / LEs N/A (CPLD macrocell architecture) —
Supply Voltage (VCCINT) 3.3 V 3.3 V (3.0 V to 3.6 V)
I/O Standards Supported 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) —
封装 208-Pin PQFP (FQFP, gull-wing) 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing)
工作温度 0 C to +70 C (commercial) 0 °C to +70 °C (commercial)
Programming In-System Programmable via JTAG (IEEE Std. 1532) —
Process Technology CMOS EEPROM, 0.30 um 0.30 µm CMOS EEPROM
RoHS 状态 Compliant Compliant
Lead-Free Yes —
Logic Capacity — 512 macrocells, 10,000 usable gates
Logic Array Blocks (LABs) — 32
Macrocells per LAB — 16
Maximum Frequency (fCNT) — 116.3 MHz
I/O Bank Count — 4 (MultiVolt)
Supported I/O Standards — 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS
Configuration — Non-volatile EEPROM, in-system programmable (ISP)
JTAG Interface — IEEE 1149.1 BST + IEEE 1532 ISP
Speed Grade — -7

数据手册与资源

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