EPM3512AQC208-7N vs EPM3512AQC208-2 对比

详细并排对比 EPM3512AQC208-7N 出自 Altera 和 EPM3512AQC208-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ 最后一次采购

规格对比

参数 EPM3512AQC208-7N EPM3512AQC208-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $41.41 $18.75
Family MAX 3000A MAX 3000A
Logic Capacity 512 macrocells, 10,000 usable gates —
Logic Array Blocks (LABs) 32 16
Macrocells per LAB 16 —
User I/Os 172 —
Propagation Delay (tPD) 7.5 ns —
Maximum Frequency (fCNT) 116.3 MHz —
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
I/O Bank Count 4 (MultiVolt) —
Supported I/O Standards 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS —
Process Technology 0.30 µm CMOS EEPROM 0.30 µm EEPROM
Configuration Non-volatile EEPROM, in-system programmable (ISP) —
JTAG Interface IEEE 1149.1 BST + IEEE 1532 ISP —
封装 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) PQFP-208 (QC)
工作温度 0 °C to +70 °C (commercial) —
RoHS 状态 Compliant Non-compliant (legacy PQFP)
Speed Grade -7 -2
Macrocells — 512
User I/O Pins — 172
Supply Voltage (Core) — 3.3 V
Output Drive Voltage — 2.5 V / 3.3 V programmable
Input Voltage Tolerance — 2.5 V / 3.3 V / 5.0 V
Program/Erase Endurance — 100 cycles (typical)
In-System Programmability — Yes (IEEE 1149.1 JTAG)
User I/O Banks — 4
工作温度范围 — Commercial (0C to +70C)
安装类型 — Surface Mount
Lead-Free — No (SnPb lead finish)
Security Bit — Yes (programmable)

数据手册与资源

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