EPM3512AQC208-7N vs EPM3512AQC208-3 对比
详细并排对比 EPM3512AQC208-7N 出自 Altera 和 EPM3512AQC208-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3512AQC208-3 - MAX 3000A CPLD, 512 Macrocells, 172 I/O, PQFP-208 | Altera
EPM3512AQC208-3 ⚠ 最后一次采购规格对比
| 参数 | EPM3512AQC208-7N | EPM3512AQC208-3 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $41.41 | $27.80 |
| Family | MAX 3000A | MAX 3000A |
| Logic Capacity | 512 macrocells, 10,000 usable gates | — |
| Logic Array Blocks (LABs) | 32 | 16 (32 macrocells each) |
| Macrocells per LAB | 16 | — |
| User I/Os | 172 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Bank Count | 4 (MultiVolt) | — |
| Supported I/O Standards | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Configuration | Non-volatile EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1149.1 BST + IEEE 1532 ISP | — |
| 封装 | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) | PQFP-208 |
| 工作温度 | 0 °C to +70 °C (commercial) | [DATA_NEEDED: industrial/commercial grade range] |
| RoHS 状态 | Compliant | [DATA_NEEDED: confirm from datasheet] |
| Speed Grade | -7 | -3 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| Maximum User I/O Pins | — | 172 |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Bank Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multiVolt) |
| In-System Programmability | — | Yes (IEEE Std. 1532 compliant) |
| Boundary-Scan Test | — | Yes (IEEE Std. 1149.1 / JTAG) |
| Program/Erase Cycles | — | 100 minimum [DATA_NEEDED: exact datasheet figure] |
| Non-Volatile Configuration | — | Yes (EEPROM-based) |
| 安装类型 | — | Surface Mount |
| MSL 等级 | — | [DATA_NEEDED: moisture sensitivity level] |