EPM3512AQI208-7 vs EPM3512AQI208-10N 对比

详细并排对比 EPM3512AQI208-7 出自 Altera 和 EPM3512AQI208-10N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AQI208-7 EPM3512AQI208-10N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $9.85 $12.90
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 10,000 —
Macro Cells 512 512
Logic Array Blocks (LABs) 16 12
Maximum Operating Frequency 116.3 MHz —
Speed Grade -7 —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD in ns] —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V —
Programmability Non-volatile, in-system programmable (IEEE Std. 1532) —
JTAG Support Yes (IEEE 1149.1 boundary scan + ISP) —
User I/O Pins [DATA_NEEDED: user I/O count for PQFP-208] —
封装 208-pin PQFP —
安装类型 Surface Mount Surface Mount
工作温度 -40C to +85C (industrial) 0C to 70C
Lead-Free / RoHS Compliant per Altera product page —
Logic Family — CMOS EEPROM-based
User I/Os — 172 (max), 208-pin package
Propagation Delay (tPD) — 10 ns
电源电压 — 3.3 V
I/O Standards — MultiVolt (2.5 V / 3.3 V / 5 V tolerant)
Package Type — PQFP-208 (FINE LINE BGA-style 256-pin land)
Pins — 256 (package), 208 used
Programming Interface — JTAG (IEEE 1149.1) / ISP (IEEE 1532)
Compliance — RoHS status unknown from data
Boundary Scan — Built-in BST (IEEE 1149.1)
Configuration Memory — On-chip EEPROM, non-volatile

数据手册与资源

浏览全部产品 创建 BOM 获取报价