EPM3512AQI208-7N vs EPM3512AQI208-7 对比

详细并排对比 EPM3512AQI208-7N 出自 Intel 和 EPM3512AQI208-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AQI208-7N EPM3512AQI208-7
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 不推荐新设计
库存状态 有库存 有库存
单价(USD) $18.45 $9.85
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Usable Gates 10,000 10,000
Macrocells 512 —
Logic Array Blocks (LABs) 16 16
Maximum Operating Frequency 116.3 MHz 116.3 MHz
Core Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) 2.5 V / 3.3 V / 5.0 V
封装 208-pin PQFP 208-pin PQFP
Programming Interface IEEE 1149.1 JTAG (in-system programmable) —
Configuration Memory EEPROM (non-volatile) —
Speed Grade 7 (7N suffix) -7
工作温度 Industrial (per 'N' suffix) -40C to +85C (industrial)
引脚数量 208 —
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant —
User I/O Pins [DATA_NEEDED: exact user I/O count for PQFP-208] [DATA_NEEDED: user I/O count for PQFP-208]
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns per speed grade 7] —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 512
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD in ns]
Programmability — Non-volatile, in-system programmable (IEEE Std. 1532)
JTAG Support — Yes (IEEE 1149.1 boundary scan + ISP)
Lead-Free / RoHS — Compliant per Altera product page

数据手册与资源

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