EPM3512AQI20810 vs EPM3512AQI208-7 对比

详细并排对比 EPM3512AQI20810 出自 Intel 和 EPM3512AQI208-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AQI20810 EPM3512AQI208-7
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $21.10 $9.85
Family MAX 3000A MAX 3000A
Macrocells 512 —
Usable Gates 10,000 10,000
Logic Array Blocks (LABs) 16 (32 macrocells each) 16
Maximum User I/O Pins 172 —
Pin-to-Pin Propagation Delay (tPD) 10 ns —
Internal fMAX (logic feedback) 87 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V —
MultiVolt I/O Interface 1.8 V / 2.5 V / 3.3 V / 5.0 V compatible —
封装 208-pin PQFP (PQ208) 208-pin PQFP
安装类型 Surface Mount Surface Mount
Process Technology 0.30 µm CMOS EEPROM —
In-System Programmability IEEE Std. 1149.1 JTAG + IEEE Std. 1532 —
工作温度 -40 °C to +85 °C (Industrial, "I" suffix) -40C to +85C (industrial)
Lead-Free / RoHS Contains lead / RoHS non-compliant (per Altera datasheet marking) Compliant per Altera product page
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 512
Maximum Operating Frequency — 116.3 MHz
Speed Grade — -7
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD in ns]
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V
Programmability — Non-volatile, in-system programmable (IEEE Std. 1532)
JTAG Support — Yes (IEEE 1149.1 boundary scan + ISP)
User I/O Pins — [DATA_NEEDED: user I/O count for PQFP-208]

数据手册与资源

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