EPM3512ATC144-10N vs EPM3512ATC144 对比

详细并排对比 EPM3512ATC144-10N 出自 Intel 和 EPM3512ATC144 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512ATC144-10N EPM3512ATC144
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 不推荐新设计
库存状态 有库存 有库存
单价(USD) $18.75 $8.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Logic Array Blocks (LABs) 16 16
Usable Gates 10000 —
Maximum User I/O 212 —
Propagation Delay (tPD) 10 ns [DATA_NEEDED: tPD in ns]
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX in MHz] —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V (MultiVolt) —
Configuration Memory Non-volatile EEPROM —
Programming Interface JTAG (IEEE 1149.1), in-system programmable —
封装 144-pin TQFP (TC144) TQFP-144 (20x20 mm)
工作温度 0C to +70C (commercial, N suffix) 0C to +70C (commercial)
RoHS 状态 [DATA_NEEDED: RoHS compliance from datasheet] Compliant (lead-free suffix variants available)
安装类型 Surface Mount Surface Mount
Lead-Free [DATA_NEEDED: lead-free status] —
Maximum User I/O Pins — 212
Core Supply Voltage — 3.3 V
Programming Technology — EEPROM (in-system programmable)
JTAG Interface — IEEE Std. 1149.1 (4-pin)
Maximum Frequency — 116 MHz
Product Terms per Macrocell — 32 (expandable)
I/O Standards — LVTTL, LVCMOS, 2.5 V/3.3 V/5 V tolerant
MSL 等级 — 3

数据手册与资源

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