EPM3512ATC256-10N vs EPM3512AFC256-7N 对比
详细并排对比 EPM3512ATC256-10N 出自 Altera 和 EPM3512AFC256-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N Obsolete规格对比
| 参数 | EPM3512ATC256-10N | EPM3512AFC256-7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $20.10 | $61.00 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 208 | — |
| 封装 | FBGA-256 (FineLine BGA, 17x17 mm, 1.0 mm pitch) | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch |
| Propagation Delay (tPD1) | 10 ns | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) | 3.3 V or 2.5 V |
| Programming Interface | JTAG (IEEE Std. 1149.1) - in-system programmable | JTAG (IEEE 1149.1) |
| 工作温度 | 0 C to +70 C (commercial, "C" suffix) | 0 C to 70 C (commercial) |
| Process Technology | 0.30 um CMOS EEPROM | CMOS EEPROM, 0.30 um |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10,000 |
| User I/Os | — | 208 |
| Logic Blocks | — | 16 (32 macrocells each) |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Internal Frequency (fMAX) | — | 116.3 MHz |
| 5V Tolerant I/O | — | Yes |
| In-System Programmability | — | IEEE Std. 1532 compliant |