EPM5016DC-20 vs EPM5064JC-1 对比

详细并排对比 EPM5016DC-20 出自 Altera 和 EPM5064JC-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5016DC-20 EPM5064JC-1
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $16.50 $18.25
Family MAX 5000 MAX 5000
Device Type EPLD (UV-Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Macrocells 16 —
Product Terms 160 —
Dedicated Inputs 7 [DATA_NEEDED: dedicated input count]
I/O Pins 8 —
Propagation Delay (tPD) 20 ns —
最大时钟频率 62.5 MHz —
Maximum Supply Voltage 5.25 V —
Nominal Supply Voltage 5.0 V —
Process Technology CMOS, UV-erasable 0.8 µm CMOS
Architecture PAL-type macrocell with Programmable Interconnect Array (PIA) —
Package Type 20-pin Ceramic DIP (Cerdip) with UV window —
Package Suffix Code DC = Ceramic DIP, Commercial —
Speed Grade -20 = 20 ns tPD —
工作温度 [DATA_NEEDED: operating temperature range] 0 °C to +70 °C (commercial, -JC suffix)
Programming Method UV erase + EPROM-style programming via Altera programming hardware Altera Logic Programmer + MasterBlaster/ByteBlasterMV
RoHS 状态 [DATA_NEEDED: RoHS compliance] Non-compliant (windowed ceramic, contains Pb in glass frit)
Macro Cells — 64
Usable Gates — 1250 (typical)
Logic Elements — 128 (Logic Array Blocks)
Maximum Operating Frequency — 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD typical/max in ns]
Supply Voltage (VCC) — 5 V nominal (4.75 V – 5.25 V)
Programmable Pins — 36 (typical I/O, 44-pin PLCC)
封装 — 44-pin PLCC (J-lead, windowed ceramic)
安装类型 — Surface Mount (PLCC socket recommended)
Erasure Method — UV-erasable through quartz window
JTAG Boundary Scan — Not supported (classic MAX architecture)
Military/Avionics SMD — 5962-01-417-3750 (QML variant: EPM5064JM/883)

数据手册与资源

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