EPM5032DC-2 vs EPM5032DC-20 对比
详细并排对比 EPM5032DC-2 出自 Altera 和 EPM5032DC-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5032DC-2 | EPM5032DC-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $8.75 | $5.05 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Usable Gates (typical) | 600 | — |
| Logic Array Blocks (LABs) | 4 | — |
| 封装 | 20-pin CDIP (Ceramic DIP) | 20-pin DIP (Windowed Ceramic, 0.3" wide) |
| Speed Grade | -2 (tPD ~25 ns, commercial) | -20 |
| Configuration Memory | EPROM (one-time programmable per generation; UV-erasable variants exist) | — |
| Supply Voltage (VCC) | 5 V (single supply, +/-5%) | 5 V |
| 工作温度 | 0C to +70C (commercial grade) | [DATA_NEEDED: commercial/industrial/military grade] |
| Programmable Pins / I/O | 20 pins (JEDEC-standard 0.300" ceramic DIP) | — |
| Programming Interface | Altera ByteBlaster / parallel-port JTAG-style ISP | — |
| Interconnect | Programmable Interconnect Array (PIA) with deterministic timing | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] | Compliant (per IC-Components listing) |
| 安装类型 | Through-Hole (DIP) | Through-Hole |
| MSL 等级 | Not applicable (through-hole hermetic ceramic) | — |
| Product Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Technology | — | UV-Erasable / OTP EPROM |
| Usable Gates | — | 600 |
| Maximum Frequency (fCNT) | — | 71.4 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Logic Blocks | — | 4 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: I/O pin count for DIP-20 variant] |
| Lead Free | — | [DATA_NEEDED: confirmed lead-free] |
| Manufacturer | — | Altera (now Intel Programmable Solutions Group) |
| Programming Method | — | Altera MAX+PLUS II / Quartus (legacy support) |