EPM5064JC-1 vs EPM5128GC 对比

详细并排对比 EPM5064JC-1 出自 Altera 和 EPM5128GC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5064JC-1 EPM5128GC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $18.25 $19.20
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) —
Macro Cells 64 —
Usable Gates 1250 (typical) 2,500
Logic Elements 128 (Logic Array Blocks) —
Maximum Operating Frequency 33.3 MHz (fCNT) —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD typical/max in ns] —
Supply Voltage (VCC) 5 V nominal (4.75 V – 5.25 V) —
Process Technology 0.8 µm CMOS CMOS, UV-erasable
Programmable Pins 36 (typical I/O, 44-pin PLCC) —
Dedicated Inputs [DATA_NEEDED: dedicated input count] —
封装 44-pin PLCC (J-lead, windowed ceramic) —
安装类型 Surface Mount (PLCC socket recommended) Through-Hole (PGA socket required)
工作温度 0 °C to +70 °C (commercial, -JC suffix) —
Erasure Method UV-erasable through quartz window —
Programming Method Altera Logic Programmer + MasterBlaster/ByteBlasterMV —
JTAG Boundary Scan Not supported (classic MAX architecture) —
RoHS 状态 Non-compliant (windowed ceramic, contains Pb in glass frit) [DATA_NEEDED: RoHS compliance]
Military/Avionics SMD 5962-01-417-3750 (QML variant: EPM5064JM/883) —
Macrocells — 128
Logic Elements / LABs — [DATA_NEEDED: LAB count]
User I/Os — 68
Package Type — WPGA (Windowed Ceramic Pin Grid Array)
Package Code — WPGA
Number of Terminals — 68
Terminal Form — PIN/PEG (through-hole PGA with alignment pegs)
Package Shape — Square
Temperature Grade — Commercial
Supply Voltage (Vcc) — 5 V
Architecture — EPLD, programmable AND/OR array with fixed OR plane
Propagation Delay (tpd) — [DATA_NEEDED: tpd in ns]
Maximum Frequency (fmax) — [DATA_NEEDED: fmax in MHz]
Programmable Security Bit — Yes
Configuration Memory — Non-volatile UV-EPROM (windowed ceramic)

数据手册与资源

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