EPM5064JC-1 vs EPM5128GC-1 对比

详细并排对比 EPM5064JC-1 出自 Altera 和 EPM5128GC-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5064JC-1 EPM5128GC-1
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $18.25 $18.95
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) UV-erasable CMOS CPLD
Macro Cells 64 —
Usable Gates 1250 (typical) 2,500
Logic Elements 128 (Logic Array Blocks) —
Maximum Operating Frequency 33.3 MHz (fCNT) 62.5 MHz
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD typical/max in ns] —
Supply Voltage (VCC) 5 V nominal (4.75 V – 5.25 V) —
Process Technology 0.8 µm CMOS —
Programmable Pins 36 (typical I/O, 44-pin PLCC) —
Dedicated Inputs [DATA_NEEDED: dedicated input count] 7
封装 44-pin PLCC (J-lead, windowed ceramic) PGA-96+ (Pin Grid Array, ceramic windowed)
安装类型 Surface Mount (PLCC socket recommended) —
工作温度 0 °C to +70 °C (commercial, -JC suffix) -40C to +85C (industrial)
Erasure Method UV-erasable through quartz window —
Programming Method Altera Logic Programmer + MasterBlaster/ByteBlasterMV UV erase + EPROM program (or device programmer)
JTAG Boundary Scan Not supported (classic MAX architecture) —
RoHS 状态 Non-compliant (windowed ceramic, contains Pb in glass frit) [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy]
Military/Avionics SMD 5962-01-417-3750 (QML variant: EPM5064JM/883) —
Macrocells — 128
Maximum User I/O Pins — 52
Nominal Supply Voltage — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Propagation Delay (tPD) — 16 ns (typical, -1 speed grade)
Technology — CMOS, UV-erasable EPROM
IOL / IOH — 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec])
Security Bit — Programmable, prevents readback
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

浏览全部产品 创建 BOM 获取报价