EPM5064LC-2 vs EPM5064JC-1 对比

详细并排对比 EPM5064LC-2 出自 Altera 和 EPM5064JC-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5064LC-2 EPM5064JC-1
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $8.40 $18.25
Device Family MAX 5000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 —
Logic Array Blocks (LABs) 4 —
Logic Elements per LAB 16 —
Number of Inputs 36 (7 dedicated + 28 I/O) —
Number of I/O Pins 28 —
Number of Flip-Flops 28 —
Propagation Delay (tPD) 45 ns —
Maximum Internal Frequency 40 MHz —
Process Technology CMOS, OTP EPROM (UV-erasable base) 0.8 µm CMOS
Programmable Polarity Yes —
Programmable Output Enable Yes, per macrocell —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V nominal (4.75 V – 5.25 V)
工作温度 -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] 0 °C to +70 °C (commercial, -JC suffix)
封装 PLCC-44 (J-Lead, plastic) 44-pin PLCC (J-lead, windowed ceramic)
安装类型 Surface Mount Surface Mount (PLCC socket recommended)
RoHS 状态 [DATA_NEEDED: not specified in source] Non-compliant (windowed ceramic, contains Pb in glass frit)
Programming Method Altera byte-wide / JTAG programmer Altera Logic Programmer + MasterBlaster/ByteBlasterMV
Family — MAX 5000
Device Type — EPLD (Erasable Programmable Logic Device)
Macro Cells — 64
Usable Gates — 1250 (typical)
Logic Elements — 128 (Logic Array Blocks)
Maximum Operating Frequency — 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD typical/max in ns]
Programmable Pins — 36 (typical I/O, 44-pin PLCC)
Dedicated Inputs — [DATA_NEEDED: dedicated input count]
Erasure Method — UV-erasable through quartz window
JTAG Boundary Scan — Not supported (classic MAX architecture)
Military/Avionics SMD — 5962-01-417-3750 (QML variant: EPM5064JM/883)

数据手册与资源

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