EPM5192AGC84-20 vs EPM5192AGC 对比

详细并排对比 EPM5192AGC84-20 出自 Altera 和 EPM5192AGC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AGC84-20 EPM5192AGC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $41.20 $56.00
Product Type Complex Programmable Logic Device (CPLD) —
Family MAX 5000 MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Macrocells 192 192
User I/O Pins 64 —
Dedicated Inputs 7 —
Logic Gates (typical) [DATA_NEEDED: typical gate count] —
Maximum Clock Frequency (fMAX) 66.7 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
封装 84-pin Ceramic Pin Grid Array (CPGA, WPGA) 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
Package Code WPGA —
Erasure Method UV-Erasable (with OTP window) —
Process Technology CMOS CMOS
Operating Temperature Grade Commercial —
电源电压 [DATA_NEEDED: VCC range] [DATA_NEEDED: VCC nominal and tolerance]
I/O Standard 5V CMOS / TTL compatible —
RoHS 状态 [DATA_NEEDED: RoHS compliance] Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
安装类型 Through-Hole (Pin Grid Array socket) Through-hole (Pin Grid Array)
Device Type — UV-Erasable / OTP Complex PLD (EPLD)
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
工作温度 — [DATA_NEEDED: operating temperature range]
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
Security Bit — Programmable security bit (per MAX 5000 family)
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

数据手册与资源

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