EPM5192AJC84-15 vs EPM5192AJC-15 对比
详细并排对比 EPM5192AJC84-15 出自 Altera 和 EPM5192AJC-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsolete规格对比
| 参数 | EPM5192AJC84-15 | EPM5192AJC-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $18.95 | $9.85 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable EPROM | — |
| 封装 | 84-pin PLCC (J84C) windowed ceramic | 84-pin PLCC (J-lead, ceramic, non-windowed) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| Programming Method | UV-erase + EPROM programming (windowed package) | — |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS 状态 | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: RoHS compliance] |
| Process Technology | CMOS EPROM | — |
| Logic Capacity | — | 100% connectivity, sum-of-products PLA architecture |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Programmability | — | UV-erasable (windowed variant) / One-Time-Programmable |
| Toolchain | — | MAX+PLUS II |
| 引脚数量 | — | 84 |
| User I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Speed Grades Available | — | -15, -20, -25 (this part: -15) |
| Configuration Memory | — | EPROM (UV-erasable) |