EPM5192LC-25 vs EPM5192LC1 对比

详细并排对比 EPM5192LC-25 出自 Altera 和 EPM5192LC1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192LC-25 EPM5192LC1
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $55.00 $17.40
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 MAX 5000
Macrocells 192 192
Logic Elements 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) —
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -25 (25 ns) —
封装 JLCC-84 (ceramic J-lead chip carrier) PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier)
安装类型 Surface Mount Surface Mount
Programmable Technology UV-erasable / OTP (EPROM-based) —
Programming Interface JTAG / Altera programming hardware (legacy) —
工作温度 0C to +70C (commercial) —
电源电压 5 V (typical, MAX 5000) —
I/O Standard TTL-compatible —
Configuration Memory Non-volatile EPROM (on-chip) —
Manufacturer Altera Corporation (now Intel PSG) —
RoHS 状态 Unknown (legacy ceramic package typically non-RoHS) [DATA_NEEDED: RoHS status]
Device Type — Complex PLD (CPLD), UV-erasable/OTP
Equivalent Gates — 3750
Dedicated Inputs — 7
User I/O Pins — 64
Nominal Supply Voltage (VCC) — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
最大时钟频率 — 50 MHz
Propagation Delay (tPD) — 40 ns
Process Technology — CMOS EPROM
Programming Method — OTP (LC plastic package); UV-erasable equivalents in JC ceramic package
Operating Temperature (Commercial 'LC') — 0 °C to 70 °C
JEDEC Package Code — S-PQCC-J84

数据手册与资源

浏览全部产品 创建 BOM 获取报价