EPM5192LC1 vs EPM5192LC-25 对比
详细并排对比 EPM5192LC1 出自 Altera 和 EPM5192LC-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192LC1 | EPM5192LC-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $17.40 | $55.00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | — |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| 封装 | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | JLCC-84 (ceramic J-lead chip carrier) |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| 最大时钟频率 | 50 MHz | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS EPROM | — |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | — |
| Operating Temperature (Commercial 'LC') | 0 °C to 70 °C | — |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | Unknown (legacy ceramic package typically non-RoHS) |
| JEDEC Package Code | S-PQCC-J84 | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Speed Grade | — | -25 (25 ns) |
| Programmable Technology | — | UV-erasable / OTP (EPROM-based) |
| Programming Interface | — | JTAG / Altera programming hardware (legacy) |
| 工作温度 | — | 0C to +70C (commercial) |
| 电源电压 | — | 5 V (typical, MAX 5000) |
| I/O Standard | — | TTL-compatible |
| Configuration Memory | — | Non-volatile EPROM (on-chip) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |