EPM570M100I5N vs EPM240M100I5N 对比

详细并排对比 EPM570M100I5N 出自 Intel 和 EPM240M100I5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM240M100I5N EPM240M100I5N - MAX II CPLD 192 MC 100MBGA | Altera

EPM240M100I5N - MAX II CPLD 192 MC 100MBGA | Altera

EPM240M100I5N ✓ 量产中

规格对比

参数 EPM570M100I5N EPM240M100I5N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $8.75 $7.95
Family MAX II MAX II CPLD
Device Type CPLD (Complex Programmable Logic Device) —
Number of Macrocells 440 —
Number of Logic Array Blocks 4 LABs (110 macrocells each) —
Maximum Operating Frequency 201.1 MHz —
Pin-to-Pin Logic Delay 5.4 ns —
User I/Os 76 —
User Flash Memory 8 Kbits —
Process Technology 0.18 µm CMOS 0.18 µm, 6-layer metal flash
Supply Voltage - Core (VCCINT) 2.5 V / 3.3 V —
Supply Voltage - I/O (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) —
Package Type 100-MBGA (Micro FBGA) —
Package Size 6 x 6 mm, 0.5 mm pitch —
安装类型 Surface Mount Surface Mount (BGA)
工作温度 -40°C to +100°C (I5 grade) -40 °C to +100 °C (industrial)
Lead-Free / RoHS Lead Free, RoHS Compliant —
Programmability In-System via JTAG (IEEE 1149.1), non-volatile —
Design Software Altera Quartus II / Quartus Prime —
Series — MAX II
Macro Cells — 192
Logic Elements — 240
Maximum Internal Frequency — 201.1 MHz
Propagation Delay (tPD) — 4.7 ns
On-die Non-volatile Memory — 8 Kbits
Core Voltage — 2.5 V / 3.3 V
I/O Bank Voltages — 1.5 V / 1.8 V / 2.5 V / 3.3 V
User I/O Pins — [DATA_NEEDED: user IO count for MBGA package]
封装 — 100-MBGA (Micro FineLine BGA)
Programming Interface — JTAG (IEEE 1149.1)
RoHS 状态 — Compliant
Lead-Free — Yes

数据手册与资源

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