EPM570M100I5N vs EPM570GM100C5N 对比

详细并排对比 EPM570M100I5N 出自 Intel 和 EPM570GM100C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM570M100I5N EPM570GM100C5N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $8.75 $10.40
Family MAX II MAX II
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Number of Macrocells 440 —
Number of Logic Array Blocks 4 LABs (110 macrocells each) —
Maximum Operating Frequency 201.1 MHz —
Pin-to-Pin Logic Delay 5.4 ns —
User I/Os 76 76
User Flash Memory 8 Kbits —
Process Technology 0.18 µm CMOS —
Supply Voltage - Core (VCCINT) 2.5 V / 3.3 V —
Supply Voltage - I/O (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) —
Package Type 100-MBGA (Micro FBGA) Micro FBGA-100 (MBGA), 6 x 6 mm, 0.5 mm pitch
Package Size 6 x 6 mm, 0.5 mm pitch —
安装类型 Surface Mount Surface Mount
工作温度 -40°C to +100°C (I5 grade) -40C to +125C (industrial)
Lead-Free / RoHS Lead Free, RoHS Compliant —
Programmability In-System via JTAG (IEEE 1149.1), non-volatile —
Design Software Altera Quartus II / Quartus Prime —
Macro Cells — 440
Logic Elements — 440
引脚数 — 100
Pin-to-Pin Delay (tPD) — 5.4 ns
Maximum Frequency — 201.1 MHz
电源电压 — 1.8 V core (MultiVolt I/O 1.5 V to 3.3 V)
Program Memory Type — Flash (non-volatile, in-system programmable)
Programming Interface — JTAG (IEEE 1149.1)
Lead Free / RoHS — Yes / Compliant
Logic Family — CMOS

数据手册与资源

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