EPM570T144I5N vs EPM570T144C5N 对比

详细并排对比 EPM570T144I5N 出自 Intel 和 EPM570T144C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM570T144I5N EPM570T144I5N - 570 LE MAX II CPLD, 144-TQFP | Intel (Altera)

EPM570T144I5N - 570 LE MAX II CPLD, 144-TQFP | Intel (Altera)

EPM570T144I5N ⚠ 最后一次采购
Intel
EPM570T144C5N EPM570T144C5N - MAX II CPLD, 570 LEs, 116 I/O | Intel

EPM570T144C5N - MAX II CPLD, 570 LEs, 116 I/O | Intel

EPM570T144C5N ✓ 量产中

规格对比

参数 EPM570T144I5N EPM570T144C5N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 有效
库存状态 有库存 有库存
单价(USD) $10.50 $9.35
Family MAX II MAX II
Logic Elements 570 LE —
Macrocells 440 440
Maximum Pin-to-Pin Delay (tPD1) 8.7 ns —
Maximum Frequency (fCNT) 304 MHz —
User Flash Memory (UFM) 8 Kbits —
Supply Voltage - Core (VCCINT) 3.0 V to 3.6 V (3.3 V typical) —
I/O Bank Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
工作温度 -40C to +100C (industrial) 0 °C to +85 °C (commercial, C5 grade)
Speed Grade I5N —
Process Technology 0.18 um CMOS, 6-layer-metal flash 0.18 µm 6-layer-metal flash
封装 TQFP-144 (22 mm x 22 mm, 0.5 mm pitch) TQFP-144 (20 × 20 mm, 0.5 mm pitch)
安装类型 Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1) / ISP IEEE 1149.1 JTAG (in-system programmable)
Boundary-Scan Test IEEE 1149.1 compliant —
RoHS 状态 Compliant Compliant
Series — MAX II Device
Logic Elements (LEs) — 570
User I/Os — 116
Internal User Flash Memory — 8 Kbit
Global Clocks — 4
Core Voltage (VCCINT) — 1.8 V (typical, internally regulated)
I/O Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank)
Maximum User I/O Pins — 116
Propagation Delay (tPD) — 5.5 ns (typical, [DATA_NEEDED: exact speed grade])
Maximum Frequency (fMAX) — 201.1 MHz
Configuration Storage — On-chip non-volatile flash
Supported I/O Standards — LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO)
Lead-Free — Yes
MSL 等级 — 3 (per JEDEC J-STD-020)
Design Software — Intel Quartus II (MAX II device support)

数据手册与资源

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