EPM7096QC100-7 vs EPM7096QI100-15 对比

详细并排对比 EPM7096QC100-7 出自 Altera 和 EPM7096QI100-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7096QC100-7 EPM7096QC100-7 - MAX 7000 CPLD, 96 Macrocells, 7.5ns | Altera

EPM7096QC100-7 - MAX 7000 CPLD, 96 Macrocells, 7.5ns | Altera

EPM7096QC100-7 ⚠ 最后一次采购
Altera
EPM7096QI100-15 EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera

EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera

EPM7096QI100-15 ⚠ 最后一次采购

规格对比

参数 EPM7096QC100-7 EPM7096QI100-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 最后采购期
库存状态 有库存 有库存
单价(USD) $31.00 $14.20
Family MAX 7000 —
Series MAX 7000 MAX 7000
Product Type CPLD (Complex Programmable Logic Device) —
Programmable Type EE PLD (EEPROM-based, in-system programmable) EE PLD (EEPROM-based, in-system programmable)
Macrocells 96 —
User I/Os 76 —
Logic Elements / Gates 1800 gates (typical) —
Pin-to-Pin Delay (tPD) 7.5 ns —
Maximum Frequency (fMAX) 125 MHz —
Supply Voltage - Internal 4.75 V to 5.25 V —
封装 / 外壳 100-BQFP (PQFP-100, 20x14 mm, 0.65 mm pitch) 100-BQFP (BQFP-100)
Supplier Device Package 100-PQFP (20x14) —
工作温度 0C to +70C (commercial) -40C to +85C (industrial, per Q-suffix)
Program Memory EEPROM (non-volatile, in-system programmable) —
Programming Interface JTAG (IEEE 1149.1) / ByteBlaster IEEE Std. 1149.1 JTAG (ISP)
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status not stated in verified data]
Device Type — CPLD - Complex Programmable Logic Device
Number of Macrocells — 96
Number of Logic Array Blocks (LABs) — 4
Number of Usable Gates — 1,800
Number of I/O Pins — 76
Maximum Propagation Delay (tPD) — 15 ns
Supply Voltage (VCC) — 4.5 V to 5.5 V
Packaging — Tray

数据手册与资源

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