EPM7128AETC100-10 vs EPM7128ATC100-10 对比
详细并排对比 EPM7128AETC100-10 出自 Intel 和 EPM7128ATC100-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 Obsolete规格对比
| 参数 | EPM7128AETC100-10 | EPM7128ATC100-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $13.85 | $4.95 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | 128 |
| User I/Os | 84 | — |
| Usable Gates | 2.5K | 2.5K |
| Logic Array Blocks (LABs) | 8 | 4 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Tolerance | 5.0 V tolerant | — |
| Program Technology | EEPROM (in-system programmable) | — |
| 封装 | 100-pin TQFP (ET) | 100-pin TQFP (TC100) |
| 工作温度 | -40C to +85C (commercial/industrial) | 0C to +70C (commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS 状态 | Compliant | [DATA_NEEDED: RoHS compliance] |
| 生命周期状态 | Obsolete (migrate to MAX II or MAX V) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX) |
| User I/O Pins | — | 68 |
| Pin-to-Pin Logic Delay | — | 4.5 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Speed Grade | — | -10 (10 ns) |
| Core Supply Voltage | — | 3.3 V |
| I/O Logic Level Support | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Program Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| 安装类型 | — | Surface Mount |