EPM7128AETC144-7N vs EPM7128BTC144-7 对比
详细并排对比 EPM7128AETC144-7N 出自 Altera 和 EPM7128BTC144-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ 量产中规格对比
| 参数 | EPM7128AETC144-7N | EPM7128BTC144-7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $39.82 | $9.85 |
| Family | MAX 7000A | MAX 7000B |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Gates | 2500 (2.5K gates) | — |
| Macro Cells | 128 | 128 |
| User I/Os | 36 (in 144-pin TQFP) | — |
| Maximum Operating Frequency | 129.9 MHz | 175 MHz (family typical) |
| Pin-to-Pin Delay | 7.5 ns | — |
| Propagation Delay (tpd) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | 2.5 V |
| Process Technology | CMOS, EEPROM-based | — |
| Programmability | In-System Programmable (ISP) via JTAG | IEEE 1149.1 JTAG (ISP) |
| Boundary-Scan Test | IEEE Std 1149.1 (JTAG) | — |
| 工作温度 | 0C to +70C (commercial) | — |
| 封装 | 144-pin TQFP | 144-pin TQFP |
| 安装类型 | Surface Mount | Surface Mount |
| Pin-Compatible With | MAX 7000S 5.0V family (144-pin TQFP) | — |
| RoHS 状态 | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | [DATA_NEEDED: lead-free status] |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 |
| User I/O Pins | — | 100 (per 144-pin TQFP package) |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Counter Frequency (fCNT) | — | 126.6 MHz |
| I/O Bank Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multiVolt) |
| Configuration Memory | — | EEPROM (non-volatile, ISP) |
| Operating Temperature (Commercial) | — | 0C to +90C |