EPM7128AETI100-7 vs EPM7128ATC100-7F 对比
详细并排对比 EPM7128AETI100-7 出自 Altera 和 EPM7128ATC100-7F 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteAltera
EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
EPM7128ATC100-7F Nrnd规格对比
| 参数 | EPM7128AETI100-7 | EPM7128ATC100-7F |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $30.10 | $9.85 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2.5K |
| User I/Os | 84 | — |
| Logic Blocks (LABs) | 8 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency | 129.9 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | IEEE Std 1149.1 boundary-scan + ISP |
| Global Clock Inputs | 4 dedicated | — |
| 封装 | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | 100-pin TQFP (14x14 mm) |
| 工作温度 | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| 安装类型 | Surface Mount | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: confirm RoHS for non-N suffix] | [DATA_NEEDED: RoHS status] |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | — |
| Device | — | EPM7128A |
| Logic Elements / Macrocells | — | 128 macrocells |
| Logic Array Blocks (LABs) | — | 8 |
| User I/O Pins | — | 84 (per MicrochipUSA) / 100 (per MAX 7000A datasheet range) |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Internal Frequency (fMAX) | — | 116.3 MHz |
| Supply Voltage - Internal | — | 3.0 V to 3.6 V (nominal 3.3 V) |
| I/O Voltage | — | 2.5 V / 3.3 V (MultiVolt) |
| Programmable Type | — | EEPROM (in-system programmable, non-volatile) |
| Process Technology | — | CMOS, EEPROM configuration |