EPM7128ATI100-10 vs EPM7128AETC100-10 对比

详细并排对比 EPM7128ATI100-10 出自 Altera 和 EPM7128AETC100-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7128ATI100-10 EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A

EPM7128ATI100-10 - 128-Macrocell 10ns 3.3V CPLD | Altera MAX 7000A

EPM7128ATI100-10 ⚠ 最后一次采购

规格对比

参数 EPM7128ATI100-10 EPM7128AETC100-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $13.85 $13.85
Series MAX 7000A —
Family MAX 7000A (MAX II of MAX 7000 series) MAX 7000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Programmable Type EE PLD (EEPROM-based, in-system programmable) —
Number of Macrocells 128 —
Number of Logic Array Blocks (LABs) 4 —
Usable Gates 2,500 2.5K
Number of I/O Pins 68 —
Propagation Delay (tPD) 10 ns —
Maximum Frequency (fMAX) 87 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typical) —
I/O Standard MultiVolt (2.5V / 3.3V / 5.0V tolerant) —
Programming Interface IEEE Std. 1149.1 JTAG (ISP) —
工作温度 -40C to +85C (Industrial, 'I' suffix) -40C to +85C (commercial/industrial)
封装 100-pin TQFP (14x14 mm) 100-pin TQFP (ET)
Process Technology CMOS EEPROM —
RoHS 状态 Non-compliant (legacy part) Compliant
安装类型 Surface Mount —
Macrocells — 128
User I/Os — 84
Logic Array Blocks (LABs) — 8
Pin-to-Pin Delay (tPD) — 10 ns
Supply Voltage (Core) — 3.3 V
I/O Tolerance — 5.0 V tolerant
Program Technology — EEPROM (in-system programmable)
JTAG Support — IEEE 1149.1 boundary-scan
生命周期状态 — Obsolete (migrate to MAX II or MAX V)

数据手册与资源

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