EPM7128EQI100-15 vs EPM7128SQI100-10N 对比

详细并排对比 EPM7128EQI100-15 出自 Altera 和 EPM7128SQI100-10N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7128EQI100-15 EPM7128SQI100-10N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $32.75 $15.90
Family MAX 7000 MAX 7000S
Device Type CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device
Macrocells 128 128
Usable Gates 2.5K 2,500 (up to 5,000 usable in family)
Logic Array Blocks (LABs) 8 (16 macrocells each) 4
User I/O Pins 84 —
Pin-to-Pin Propagation Delay (tPD) 15 ns —
Maximum Operating Frequency 76.9 MHz 100 MHz
Supply Voltage (VCCINT/VCCIO) 4.75 V to 5.25 V (5 V nominal) —
工作温度 -40 °C to +85 °C (industrial grade, "I" suffix) -40C to +85C (Industrial grade, 'I' suffix)
封装 100-pin PQFP (BQFP, 14x20 mm) 100-pin PQFP (Plastic Quad Flat Pack)
安装类型 Surface Mount Surface Mount
Programming Technology EEPROM (non-volatile, in-system programmable) —
Boundary Scan IEEE 1149.1 (JTAG) compliant —
RoHS 状态 Compliant (lead-free; verify per lot) —
Manufacturer Altera (now Intel FPGA) —
Maximum User I/Os — 84
Pin-to-Pin Logic Delay (tPD) — 10 ns
Counter Frequency (family max) — 175.4 MHz
Supply Voltage - Core (VCCINT) — 5.0 V
Supply Voltage - I/O (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multiVolt)
Technology — CMOS, EEPROM-based configuration
Programming Interface — JTAG (IEEE Std. 1149.1) / ByteBlaster
RoHS Compliance — Compliant (lead-free, 'N' suffix)

数据手册与资源

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