EPM7128SQI100-10N vs EPM7128STI100-10N 对比

详细并排对比 EPM7128SQI100-10N 出自 Intel 和 EPM7128STI100-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7128SQI100-10N EPM7128STI100-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $15.90 $9.85
Family MAX 7000S MAX 7000S
Device Type CPLD - Complex Programmable Logic Device —
Macrocells 128 128
Usable Gates 2,500 (up to 5,000 usable in family) 2,500 (up to 5,000 family max)
Logic Array Blocks (LABs) 4 8
Maximum User I/Os 84 —
Pin-to-Pin Logic Delay (tPD) 10 ns 10 ns
Maximum Operating Frequency 100 MHz —
Counter Frequency (family max) 175.4 MHz —
Supply Voltage - Core (VCCINT) 5.0 V —
Supply Voltage - I/O (VCCIO) 2.5 V / 3.3 V / 5.0 V (multiVolt) —
Technology CMOS, EEPROM-based configuration —
封装 100-pin PQFP (Plastic Quad Flat Pack) 100-pin TQFP
安装类型 Surface Mount Surface Mount
工作温度 -40C to +85C (Industrial grade, 'I' suffix) -40C to +85C (Industrial)
Programming Interface JTAG (IEEE Std. 1149.1) / ByteBlaster —
RoHS Compliance Compliant (lead-free, 'N' suffix) —
Architecture — CMOS EEPROM-based CPLD
Maximum User I/O — 84
Maximum Counter Frequency — 175.4 MHz
Supply Voltage (VCC) — 5 V
In-System Programmability — Yes (JTAG IEEE 1149.1)
JTAG Boundary-Scan — Yes (BST)
MSL 等级 — [DATA_NEEDED: MSL level]
RoHS 状态 — [DATA_NEEDED: RoHS status]
Open-Drain I/O Option — Available (per MAX 7000A feature set)

数据手册与资源

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