EPM7160SLC84-10 vs EPM7160SLC84-15 对比
详细并排对比 EPM7160SLC84-10 出自 Altera 和 EPM7160SLC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7160SLC84-10 | EPM7160SLC84-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $35.77 | $10.80 |
| Family | MAX 7000S | MAX 7000 |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 4 | — |
| Maximum User I/O Pins | 64 | 64 |
| Usable Gates | 3,200 | 3,200 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) | — |
| Technology | EEPROM-based CMOS | CMOS, EEPROM configuration |
| 封装 | 84-Pin PLCC (J-Lead) | — |
| 安装类型 | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| 工作温度 | 0C to +70C (Commercial) | 0 C to 70 C |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | Not RoHS compliant (contains lead, SnPb finish typical) |
| Maximum Propagation Delay | — | 15 ns |
| Supply Voltage (VCCINT/VCIO) | — | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Level | — | Configurable 3.3 V or 5 V |
| Package Type | — | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) |
| Terminal Pitch | — | 1.270 mm |
| Programming Interface | — | JTAG (IEEE 1149.1) in-system programmable |
| Lifecycle | — | Obsolete / last-time-buy (per Altera/Intel PDN) |