EPM7160SLC84-15 vs EPM7160ELC84-12 对比

详细并排对比 EPM7160SLC84-15 出自 Altera 和 EPM7160ELC84-12 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7160ELC84-12 EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera

EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera

EPM7160ELC84-12 ⚠ 最后一次采购

规格对比

参数 EPM7160SLC84-15 EPM7160ELC84-12
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $10.80 $11.10
Family MAX 7000 —
Macrocells 160 —
Usable Gates 3,200 —
Maximum Propagation Delay 15 ns —
Maximum User I/O Pins 64 —
Supply Voltage (VCCINT/VCIO) 4.75 V to 5.25 V (5 V nominal) —
I/O Logic Level Configurable 3.3 V or 5 V —
Technology CMOS, EEPROM configuration —
Package Type PLCC-84 (PQCC84, JEDEC S-PQCC-J84) —
Terminal Pitch 1.270 mm —
安装类型 Surface Mount (PLCC socket or direct solder) Surface Mount
工作温度 0 C to 70 C 0C to +70C (commercial)
Programming Interface JTAG (IEEE 1149.1) in-system programmable —
RoHS 状态 Not RoHS compliant (contains lead, SnPb finish typical) [DATA_NEEDED: RoHS status]
Lifecycle Obsolete / last-time-buy (per Altera/Intel PDN) —
Manufacturer — Altera (Intel PSG)
Series — MAX 7000 (MAX 7000E)
Programmable Type — EE PLD (EEPROM)
Number of Macrocells — 160
Number of Logic Array Blocks (LABs) — 4
Number of Usable Gates — 3,200
Number of I/O (max) — 68
Number of I/O (per package) — 64
Propagation Delay tpd(1) max — 12 ns
Counter Frequency (max) — 90.9 MHz
Voltage Supply - Internal — 4.75 V to 5.25 V (5 V nominal)
封装 / 外壳 — 84-LCC (J-Lead)
Supplier Device Package — 84-PLCC (29.31 x 29.31 mm)
In-System Programmability — Yes (IEEE 1149.1 JTAG)

数据手册与资源

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