EPM7160SLC84-15 vs EPM7160SLC84-6 对比
详细并排对比 EPM7160SLC84-15 出自 Altera 和 EPM7160SLC84-6 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7160SLC84-15 | EPM7160SLC84-6 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.80 | $15.86 |
| Family | MAX 7000 | MAX 7000S |
| Macrocells | 160 | 160 |
| Usable Gates | 3,200 | 3.2K |
| Maximum Propagation Delay | 15 ns | — |
| Maximum User I/O Pins | 64 | — |
| Supply Voltage (VCCINT/VCIO) | 4.75 V to 5.25 V (5 V nominal) | — |
| I/O Logic Level | Configurable 3.3 V or 5 V | — |
| Technology | CMOS, EEPROM configuration | — |
| Package Type | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) | — |
| Terminal Pitch | 1.270 mm | — |
| 安装类型 | Surface Mount (PLCC socket or direct solder) | Surface Mount (J-Lead) |
| 工作温度 | 0 C to 70 C | [DATA_NEEDED: commercial vs industrial grade] |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | — |
| RoHS 状态 | Not RoHS compliant (contains lead, SnPb finish typical) | Compliant |
| Lifecycle | Obsolete / last-time-buy (per Altera/Intel PDN) | — |
| Device Type | — | EE PLD (CPLD) |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| User I/O Pins | — | 36 (also reported as 64 depending on source) |
| Pin-to-Pin Delay (tPD) | — | 6 ns (speed grade -6) |
| Counter Frequency (fCNT) | — | 149.3 MHz |
| 电源电压 | — | 4.75 V to 5.25 V (single 5 V supply) |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (5.0 V ISP via JTAG) |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| MultiVolt I/O | — | Yes (mixed-voltage interface) |
| 封装 | — | 84-pin PLCC (29.31 x 29.31 mm) |