EPM7160SLC84-15 vs EPM9400LC84-20 对比
详细并排对比 EPM7160SLC84-15 出自 Altera 和 EPM9400LC84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM7160SLC84-15 | EPM9400LC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.80 | $38.50 |
| Family | MAX 7000 | MAX 9000 |
| Macrocells | 160 | 400 |
| Usable Gates | 3,200 | 8,000 (6,000 to 12,000 typical range) |
| Maximum Propagation Delay | 15 ns | — |
| Maximum User I/O Pins | 64 | — |
| Supply Voltage (VCCINT/VCIO) | 4.75 V to 5.25 V (5 V nominal) | — |
| I/O Logic Level | Configurable 3.3 V or 5 V | — |
| Technology | CMOS, EEPROM configuration | — |
| Package Type | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) | — |
| Terminal Pitch | 1.270 mm | — |
| 安装类型 | Surface Mount (PLCC socket or direct solder) | Surface Mount (PLCC socket or SMT land pattern) |
| 工作温度 | 0 C to 70 C | Commercial (0C to +70C) - assumed from -20 speed grade |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | — |
| RoHS 状态 | Not RoHS compliant (contains lead, SnPb finish typical) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete / last-time-buy (per Altera/Intel PDN) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based |
| Flip-Flops | — | 580 |
| Maximum User I/O | — | 55 |
| Pin-to-Pin Propagation Delay | — | 20 ns (speed grade -20) |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (configurable) |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| 封装 | — | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Process Technology | — | CMOS EEPROM |