EPM7192EGI160-20 vs EPM7192EGM160-20 对比
详细并排对比 EPM7192EGI160-20 出自 Intel 和 EPM7192EGM160-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 Obsolete规格对比
| 参数 | EPM7192EGI160-20 | EPM7192EGM160-20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $264.10 | $15.60 |
| Family | MAX 7000 | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE CMOS CPLD (Electrically Erasable) |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 4 | — |
| Pin-to-Pin Delay (tpd) | 20 ns | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE Std. 1149.1) | — |
| 封装 | 160-pin CPGA (Ceramic Pin Grid Array) | PGA-160 (160-pin Pin Grid Array) |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| RoHS 状态 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Programming Interface | JTAG (ByteBlaster / USB-Blaster compatible) | — |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates | — | 600 to 5,000 |
| Maximum User I/O Pins | — | 120 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Pin-to-Pin Propagation Delay | — | 20 ns |
| Counter Frequency (max) | — | 175.4 MHz |
| I/O Standards | — | 3.3 V or 5 V configurable |
| Global Clock Inputs | — | 2 (GCLK1, GCLK2) |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Program/Erase Endurance | — | 100 cycles (EEPROM) |
| 工作温度 | — | -40C to +125C (industrial) |
| Technology Node | — | CMOS, second-generation MAX architecture |