EPM7256AETC100-10N vs EPM7256AEQI208-7N 对比
详细并排对比 EPM7256AETC100-10N 出自 Altera 和 EPM7256AEQI208-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7256AETC100-10N - 256-Macro MAX 7000A CPLD, 10ns, TQFP-100 | Intel (Altera)
EPM7256AETC100-10N Obsolete
规格对比
| 参数 | EPM7256AETC100-10N | EPM7256AEQI208-7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $13.10 | $0.00 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | 5,000 |
| Maximum User I/Os | 84 | — |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Operating Frequency | 125 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5.0 V | — |
| Programmability | EEPROM, in-system via JTAG (IEEE 1149.1) | — |
| 封装 | 100-pin TQFP | 208-pin PQFP (FQFP) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度范围 | 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] | — |
| Process Technology | 0.30 µm EEPROM | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| RoHS 状态 | [DATA_NEEDED: not confirmed in provided data] | Compliant (N suffix) |
| Lead-Free / Pb-Free | [DATA_NEEDED: not confirmed in provided data] | — |
| Macrocells | — | 256 |
| User I/O Pins | — | 164 |
| Logic Array Blocks | — | 16 |
| Pin-to-Pin Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Internal Frequency | — | 126.6 MHz |
| 电源电压 | — | 3.3 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Number of Terminals | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Industrial |
| Speed Grade | — | -7 |
| Lead Finish | — | [DATA_NEEDED: lead finish] |