EPM7256AETC144-10 vs EPM7128AETC144-10 对比

详细并排对比 EPM7256AETC144-10 出自 Intel 和 EPM7128AETC144-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7256AETC144-10 EPM7128AETC144-10
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $31.40 $21.70
Family MAX 7000A MAX 7000A
Series EPM7256AE —
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 256 —
Usable Gates 5,000 2,500
Logic Array Blocks (LABs) 16 8
Maximum User I/Os 36 36
Dedicated Inputs 16 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Operating Frequency (fMAX) 95.2 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V (5.0 V tolerant inputs on A-series) —
封装 144-pin TQFP (TQFP-144) 144-pin TQFP (also referred to as LQFP-144)
工作温度 0C to +70C (commercial) 0C to +70C (Commercial)
Programming Interface JTAG (IEEE 1149.1) + Fast Passive Serial JTAG (IEEE Std. 1149.1) and ByteBlaster
Non-Volatile Memory EEPROM-based —
RoHS 状态 [DATA_NEEDED: rohs_status] [DATA_NEEDED: rohs status from manufacturer]
Macrocells — 128
Pin-to-pin Logic Delay (tPD) — 10 ns
Maximum Internal Counter Frequency — 98 MHz
Supply Voltage (Core) — 3.3 V
I/O Voltage Tolerance — 2.5 V / 3.3 V / 5 V
Non-volatile Memory — EEPROM, instant-on
Global Clocks / Global OE — 2 / 2
安装类型 — Surface Mount
MSL 等级 — MSL 3 (per JEDEC J-STD-020)

数据手册与资源

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