EPM7256SQI208-10 vs EPM7256SQC208-7 对比

详细并排对比 EPM7256SQI208-10 出自 Altera 和 EPM7256SQC208-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7256SQI208-10 EPM7256SQC208-7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $0.40 $0.00
Device Family MAX 7000 (EPM7256) MAX 7000S (EPM7256S)
Macrocells 256 256
Usable Gates 5000 5,000
Logic Array Blocks 16 —
Maximum User I/O Pins 164 —
Propagation Delay (tPD) 10 ns 7.5 ns
Supply Voltage Range 4.5 V to 5.5 V —
Technology CMOS EEPROM —
Configuration Memory EEPROM (non-volatile) —
In-System Programmable Yes (IEEE 1149.1 JTAG) —
封装 208-pin PQFP (QFP208) 208-pin PQFP (28 x 28 mm, 0.5 mm pitch)
Package Body Material Plastic/Epoxy —
Terminal Form Gull Wing —
工作温度范围 -40 C to +85 C (Industrial) Commercial (0C to +70C)
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
JESD-30 Package Code S-PQFP-G208 —
JESD-609 Terminal Finish Code E3 —
User I/O Pins — 164
Maximum Operating Frequency (fMAX) — 128.2 MHz
Supply Voltage (VCC) — 5.0 V
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Minimum DC Input Voltage — -0.5 V
Input Undershoot Tolerance — -2.0 V for <100 mA, <20 ns
Speed Grade — -7 (7.5 ns)
MSL 等级 — [DATA_NEEDED: MSL level]
Logic Levels — 5.0 V CMOS/TTL compatible

数据手册与资源

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