EPM7256SRC208-15N vs EPM7256SQC208-15 对比

详细并排对比 EPM7256SRC208-15N 出自 Altera 和 EPM7256SQC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7256SRC208-15N EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera

EPM7256SRC208-15N Obsolete

规格对比

参数 EPM7256SRC208-15N EPM7256SQC208-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $27.20 $3.65
Series MAX 7000S EPM7256
Macrocells 256 256
Usable Gates 5,000 5000
User I/O Pins 164 164
Logic Array Blocks (LABs) 16 16
Pin-to-Pin Delay (tPD) 15 ns 15 ns
Maximum Counter Frequency 76.9 MHz —
电源电压 5 V —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
封装 208-pin RQFP (PowerQuad Flat Pack) 208-pin PQFP (28x28 mm)
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (commercial) —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
I/O Standard 5 V TTL/CMOS compatible —
RoHS 状态 Compliant (N suffix) Contains lead / RoHS non-compliant (per third-party listing)
Lead Free Yes (N suffix) —
MSL 等级 [DATA_NEEDED: MSL level] —
Number of Terminals 208 —
Family — MAX 7000S
Device Type — CPLD (Complex Programmable Logic Device)
Supply Voltage (VCCINT) — 4.75 V to 5.25 V
工作温度范围 — 0 C to +70 C (Commercial)
Programmable Power Mode — Yes (per-macrocell turbo-bit)
JTAG (IEEE 1149.1) Boundary-Scan — Yes
In-System Programmability (ISP) — Yes
Lead-Free Status — Contains lead

数据手册与资源

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