EPM9320RC208-10 vs EPM9320ARC208-10 对比

详细并排对比 EPM9320RC208-10 出自 Altera 和 EPM9320ARC208-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM9320ARC208-10 EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 ⚠ 最后一次采购

规格对比

参数 EPM9320RC208-10 EPM9320ARC208-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $26.40 $21.40
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 6,000 6,000
Macrocells 320 320
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
封装 208-pin RQFP (RC) RQFP-208 (Power Quad Flat Pack)
工作温度 Commercial (0C to +70C) - 'C' suffix [DATA_NEEDED: operating temperature range]
电源电压 5 V 5.0 V
Speed Grade -10 —
Programming Interface JTAG (ByteBlaster/BitBlaster) —
Non-volatile Configuration Yes (EPROM/EEPROM based) —
Design Tool Support MAX+PLUS II, Quartus (legacy) —
RoHS 状态 ROHS3 Compliant (per fpgalink listing) [DATA_NEEDED: RoHS compliance status]
湿敏等级(MSL) 3 (168 Hours) —
Lead Time 1-7 days (per fpgalink listing) —
Device Family — MAX 9000
Product Type — CPLD (Complex Programmable Logic Device)
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency — 144.9 MHz
Logic Blocks (LABs) — 16
Programmability — EEPROM, in-system programmable via JTAG
JTAG Support — IEEE Std. 1149.1 compliant
Speed/Power Optimization — Per-macrocell programmable, 50% power mode available
安装类型 — Surface Mount

数据手册与资源

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