EPM9320RC208-15N vs EPM9320ARC208-10 对比

详细并排对比 EPM9320RC208-15N 出自 Intel 和 EPM9320ARC208-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM9320ARC208-10 EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

EPM9320ARC208-10 ⚠ 最后一次采购

规格对比

参数 EPM9320RC208-15N EPM9320ARC208-10
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $0.00 $21.40
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 6,000 6,000
Macro Cells 320 —
Flip-Flops 484 —
Configurable I/O Lines 128 —
Propagation Delay (tPD) 15 ns —
最大时钟频率 117.6 MHz —
电源电压 5.0 V 5.0 V
I/O Voltage Compatibility 3.3 V or 5 V —
Configuration Technology CMOS EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG —
封装 208-pin RQFP (PowerQuad Flat Pack) RQFP-208 (Power Quad Flat Pack)
Terminal Pitch 0.5 mm —
工作温度范围 0C to +70C (commercial) —
安装类型 Surface Mount Surface Mount
Packaging Tray —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Device Family — MAX 9000
Product Type — CPLD (Complex Programmable Logic Device)
Macrocells — 320
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency — 144.9 MHz
Logic Blocks (LABs) — 16
Programmability — EEPROM, in-system programmable via JTAG
JTAG Support — IEEE Std. 1149.1 compliant
Speed/Power Optimization — Per-macrocell programmable, 50% power mode available
工作温度 — [DATA_NEEDED: operating temperature range]

数据手册与资源

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