EPM9320RC208-20 vs EPM9320RI208-20N 对比
详细并排对比 EPM9320RC208-20 出自 Altera 和 EPM9320RI208-20N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9320RC208-20 | EPM9320RI208-20N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $21.90 | $0.00 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| Usable Gates | 6,000 | — |
| Maximum I/O Pins | 132 | — |
| Propagation Delay (tPD max) | 20 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Programming Technology | EEPROM, in-system programmable (ISP) | — |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) | — |
| 工作温度 | 0 °C to 70 °C (commercial) | — |
| 封装 | 208-RQFP, exposed pad (208-BFQFP) | 208-pin PQFP (Plastic Quad Flat Pack) |
| 安装类型 | Surface Mount | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 3rd generation | — |
| Process Technology | CMOS, 5.0 V EEPROM | — |
| Reprogrammability | Yes, unlimited ISP cycles | — |
| Device Family | — | MAX 9000 (EPM9320) |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V configurable |
| Package Lead Pitch | — | 0.500 mm |
| Number of Terminals | — | 208 |
| 工作温度范围 | — | -40C to +85C (Industrial) |
| In-System Programmability | — | Yes, 5.0 V ISP via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Configuration Memory | — | EEPROM (non-volatile) |
| Dedicated Input Pins | — | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | — | -0.5 V |
| Minimum DC Input on Dedicated Inputs | — | -0.3 V |
| Input Undershoot/ Overshoot | — | -2.0 V / 7.0 V for <20 ns (no-load) |
| RoHS 状态 | — | [DATA_NEEDED: RoHS status] |