EPM9320RC208-20N vs EPM9400RC208-20 对比

详细并排对比 EPM9320RC208-20N 出自 Altera 和 EPM9400RC208-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320RC208-20N EPM9400RC208-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $60.49
Device Family MAX 9000 —
Logic Type Complex Programmable Logic Device (CPLD) —
Usable Gates 6,000 8,000
Macro Cells 320 400
Logic Array Blocks 20 —
Maximum Pin-to-Pin Delay (tPD) 20 ns —
Maximum Operating Frequency 100 MHz 100 MHz
电源电压 5.0 V —
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG —
User I/O Pins 168 —
封装 208-pin RQFP (PowerQuad II) 208-pin RQFP (28x28 mm)
安装类型 Surface Mount Surface Mount
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Lead Finish [DATA_NEEDED: lead finish] —
MSL 等级 [DATA_NEEDED: MSL level] [DATA_NEEDED: moisture sensitivity level]
Family — MAX 9000
Programmable Type — In System Programmable (ISP)
Pin-to-Pin Propagation Delay — 20 ns
Supply Voltage (Internal) — 4.75 V to 5.25 V
Configuration Technology — EEPROM-based (non-volatile)
JTAG Interface — IEEE Std. 1149.1
Supplier Device Package — 208-RQFP
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Speed Grade — -20 (20 ns)

数据手册与资源

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