EPM9480RC240-15 vs EPM9560RC-15 对比

详细并排对比 EPM9480RC240-15 出自 Altera 和 EPM9560RC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9480RC240-15 EPM9560RC-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $91.68 $30.10
Programmable Type In System Programmable (ISP) —
Device Family MAX 9000 —
Macro Cells 480 —
Usable Gates 12,000 12,000
Pin-to-Pin Delay (tPD) 15 ns —
Internal Supply Voltage 4.75 V to 5.25 V —
Configuration Technology EEPROM-based (non-volatile) —
JTAG Interface IEEE Std. 1149.1 —
封装 240-pin RQFP (32x32 mm) 240-pin RQFP (32x32 mm)
Supplier Device Package 240-RQFP (32x32) —
安装类型 Surface Mount Surface Mount
工作温度 [DATA_NEEDED: operating temperature range] 0 C to +70 C (commercial)
Number of I/O Pins [DATA_NEEDED: user I/O count] —
RoHS 状态 RoHS non-compliant [DATA_NEEDED: RoHS status]
Lead Free Status [DATA_NEEDED: lead free status] —
Logic Architecture Multiple Array MatriX (MAX) third-generation —
Supply Voltage (5.0 V nominal) 5.0 V —
Family — MAX 9000
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 560
Logic Array Blocks (LABs) — 16 (40 macrocells each)
Maximum User I/O Pins — 191
Pin-to-Pin Delay (tPD1) — 15 ns
Supply Voltage (VCCINT) — 4.75 V to 5.25 V (5.0 V nominal)
Programming Interface — IEEE Std. 1149.1 JTAG (ISP)
Process Technology — CMOS EEPROM
Architecture — Multiple Array MatriX (MAX) - third generation
In-System Programmability — Yes (5.0 V ISP via JTAG)

数据手册与资源

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